tp2510 features low threshold -2.4v max. high input impedance low input capacitance 125pf max. fast switching speeds low on resistance free from secondary breakdown low input and output leakage complementary n and p-channel devices applications logic level interfaces ideal for ttl and cmos solid state relays battery operated systems photo voltaic drives analog switches general purpose line drivers telecom switches ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? general description these low threshold enhancement-mode (normally-off) tran- sistors utilize a vertical dmos structure and supertexs well- proven silicon-gate manufacturing process. this combination produces devices with the power handling capabilities of bipolar transistors and with the high input impedance and positive temperature coef? cient inherent in mos devices. characteristic of all mos structures, these devices are free from thermal runaway and thermally-induced secondary breakdown. supertexs vertical dmos fets are ideally suited to a widerange of switching and amplifying applications where very low threshold voltage, high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired. switching waveforms and test circuit low threshold p-channel enhancement mode vertical dmos fets thermal characteristics package i d continuous ? (ma) i d pulsed (a) power dissipation @ t a = 25 o c (w) jc ( o c/w) jc ( o c/w) i dr ? (ma) i drm (a) to-243aa -480 -2.5 1.6 ? 15 78 ? -480 -2.5 ? i d (continuous) is limited by max rated t j . ? mounted on fr5 board, 25mm x 25mm x 1.57mm. 90% 10% 90% 90% 10% 10% pulse generator v dd r l output d.u.t. t (on) t d(on) t (off) t d(off) t f t r input input output 0v v dd r gen 0v -10v
2 tp2510 ordering information device package options bv dss /bv dgs (v) r ds(on) () v gs(th) (max) (v) i d(on) (min) (a) to-243aa (sot-89) die* tp2510 TP2510N8-G tp2510nd -100 3.5 -2.4 -1.5 * mil visual screening available. -g indicates package is rohs compliant (green) pin con? guration parameter value drain-to-source voltage bv dss drain-to-gate voltage bv dgs gate-to-source voltage 20v operating and storage temperature -55c to +150c soldering temperature* 300c * distance of 1.6 mm from case for 10 seconds. symbol parameter min typ max units conditions electrical characteristics (@25c unless otherwise speci? ed ) absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied. continuous operation of the device at the absolute rating level may affect device reliability. all voltages are referenced to device ground. bv dss drain-to-source breakdown voltage -100 - - v v gs = 0v, id = -2.0ma v gs(th) gate threshold voltage -1.0 - -2.4 v v gs = v ds , id= -1.0ma ?v gs(th) change in v gs(th) with temperature - - 5.0 mv/ o cv gs = v ds , id= -1.0ma i gss gate body leakage - - -100 na v gs = 20v, v ds = 0v i dss zero gate voltage drain current - --10av gs = 0v, v ds = max rating - -1.0 ma v gs = 0v, v ds = 0.8 max rating, t a = 125c i d(on) on-state drain current -0.4 -0.6 - a v gs = -5.0v, v ds = -25v -1.5 -2.5 - v gs = -10v, v ds = -25v r ds(on) static drain-to-source on-state resistance - 5.0 7.0 v gs = -5.0v, id = -250ma 2.0 3.5 v gs = -10v, id = -0.75a ?r ds(on) change in r ds(on) with temperature - - 1.7 %/ o cv gs = -10v, id = -0.75a g fs forward transconductance 300 360 - mmho v ds = -25v, id = -0.75a c iss input capacitance - 80 125 pf v gs = 0v, v ds = -25v, f = 1.0 mhz c oss common source output capacitance - 40 70 c rss reverse transfer capacitance - 10 25 t d(on) turn-on delay time - - 10 ns v dd = -25v, i d = -1.0a, r gen = 25? t r rise time - - 15 t d(off) turn-off delay time - - 20 t f fall time - - 15 v sd diode forward voltage drop - - -1.8 v v gs = 0v, i sd = -1.0a t rr reverse recovery time - 300 - ns v gs = 0v, i sd = -1.0a absolute maximum ratings notes: 1. all d.c. parameters 100% tested at 25c unless otherwise stated. (pulse test: 300s pulse, 2% duty cycle.) 2. all a.c. parameters sample tested. to-243aa (sot-89) (top view) gate drain sink drain product marking tp5aw w = code for week sealed = green packaging to-243aa (sot-89) n8
3 tp2510 typical performance curves output characteristics -5 -4 -3 -2 -1 0 0 -10 -20 -30 -50 -40 saturation characteristics -5 -4 -3 -2 -1 0 0 -2 -4 -6 -10 -8 maximum rated safe operating area -0.1 -100 -10 -1.0 -10 -1.0 -0.1 -0.01 thermal response characteristics thermal resistance (normalized) 1.0 0.8 0.6 0.4 0.2 0.001 10 0.01 0.1 1 t p (seconds) transconductance vs. drain current 0.5 0.4 0.3 0.2 0.1 0 0 -2.5 -0.5 -1.0 -1.5 -2.0 power dissipation vs. ambient temperature 0 150 100 50 2.0 1.0 0 125 75 25 to-243aa(pulsed) v gs = -10v -6v -4v 0 to-243aa (dc) -3v to-243aa -8v -3v -4v -8v -6v v ds = -25v t a = -55c t a = 25c t a = 125c t a = 25c to-243aa t a = 25c p d = 1.6w v ds (volts) i d (amperes) i d (amperes) v ds (volts) v gs = -10v g fs (siemens) i d (amperes) t a (c) p d (watts) v ds (volts) i d (amperes)
4 tp2510 typical performance curves gate drive dynamic characteristics on-resistance vs. drain current transfer characteristics capacitance vs. drain-to-source voltage 200 c (picofarads) 0 -10 -20 -30 -40 100 0 -2-4-6-8-10 -5 -4 -3 -2 -1 0 0 -50 0 50 100 150 1.1 1.0 0.9 10 8 6 4 2 0 1.4 1.2 1.0 0.8 0.6 0.4 2.0 1.6 1.2 0.8 0.4 0 -10 -8 -6 -4 -2 0 0 1.0 2.0 -50 0 50 100 150 v ds = -40v v ds = -10v v gs = -5v v gs = -10v t a = -55 c 0 -0.8 -1.6 -2.4 -4.0 -3.2 f = 1mhz 71 pf r ds (on) @ -10v, -0.75a 150 50 0 142 pf 150 c 25 c r ds(on) (ohms) bv dss (normalized) t j ( c) i d (amperes) bv dss variation with temperature t j ( c) v gs(th) (normalized) r ds(on) (normalized) v (th) and r ds variation with temperature v gs (volts) i d (amperes) v ds = -25v v (th) @ -1ma q g (nanocoulombs) v gs (volts) v ds (volts) c iss c oss c rss
5 tp2510 3-lead to-243aa (sot-89) package outline (n8) symbol a b b1 c d d1 e e1 e e1 h l dimensions (mm) min 1.40 0.44 0.36 0.35 4.40 1.62 2.29 2.13 1.50 bsc 3.00 bsc 3.94 0.89 nom-------- -- max 1.60 0.56 0.48 0.44 4.60 1.83 2.60 2.29 4.25 1.20 jedec registration to-243, variation aa, issue c, july 1986. drawings not to scale . 4 2 1 d e h e1 e b1 3 d1 e1 a c l top view side view b (the package drawing(s) in this data sheet may not re? ect the most current speci? cations. for the latest package outline information go to http://www.supertex.com/packaging.html .) doc.# dsfp - tp2510 a082307
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